Engineering Challenges in Scaling from NISQ to Universal Fault–Tolerant Quantum Computers
QCE21 Workshop Week 12
Wednesday, October 20, 2021, 10:45–16:45 Mountain Time (MDT) – UTC-6
Modern day quantum processors are beginning to demonstrate quantum advantage for some specific use cases. However, significant further progress is needed to achieve practical advantage in quantum computing. To this end, the focus remains squarely on rapidly and substantially scaling the size of quantum processors, with many leading cloud providers having announced that they will deploy quantum computers with more than one thousand qubits in the next five years. To achieve this important milestone, there are many engineering challenges that must be overcome. In superconducting and spin qubit architectures, the challenges begin in designing and fabricating large quantum processors. The next major topic will be the improvements in classical hardware (environment, control systems and cryogenic components) that are necessary to scale quantum processors. Finally, we will touch on the software required to characterize, validate and verify the performance of these quantum processors efficiently. This workshop will provide an overview of how these diverse challenges are being addressed by world leading experts from academia and industry and provide a roadmap for how to achieve the large fault-tolerant quantum processors that are required to solve today’s intractable problems.
PROGRAM AT A GLANCE:
*Mountain Time (MDT) – UTC-6
|10:50||Matt Reagor||Quantum computers from superconducting qubits|
|11:15||Will Oliver||Quantum Engineering of Superconducting Qubits|
|11:55||Jörgen Stenarson||Cryogenic Electronics for Scalable Quantum Computing Part I|
|13:00||Arsalan Pourkabirian||Cryogenic Electronics for Scalable Quantum Computing Part II|
|13:20||Russell Lake||Dilution refrigerator quantum measurement systems|
|13:55||Nizar Messaoudi||Direct Digital Upconversion for High Fidelity Control of Qubits|
|15:15||Joseph Emerson||Scalable error diagnostics, benchmarking and error suppression for large quantum processors|
|15:55||All||Round panel Discussion|
|16:35||Final comments/ question|
Quantum computers from superconducting qubits
Speaker: Dr. Matt Reagor – Rigetti Computing
Quantum computers powered by hundreds of gate based, superconducting qubits are just over the horizon. Several groups have already announced activities on quantum processors (QP) of 50 qubits or more. The systems containing these processors will be of fundamental importance in quantum algorithm development, on our path toward quantum advantage in the noisy intermediate scale quantum (NISQ) era. Quantum advantage is the point at which quantum computers can solve a problem faster, cheaper, or more accurately than their classical counterparts, which is likely to be accomplished before fully fault tolerant machines are available. This talk will address the trade-offs in the design of hybrid quantum-classical computing systems based on gate based superconducting processors approaching 100 qubits.
Matt Reagor is VP of Applications Research at Rigetti Computing and CTO of SQMS, a National QIS Research Center. Matt’s work concerns efficient programming models of superconducting qubit hardware in pursuit of practical quantum-accelerated workloads.
Quantum Engineering of Superconducting Qubits
Speaker: Professor William D. Oliver – Massachusetts Institute of Technology
Superconducting qubits are coherent artificial atoms assembled from electrical circuit elements and microwave optical components. Their lithographic scalability, compatibility with microwave control, and operability at nanosecond time scales all converge to make the superconducting qubit a highly attractive candidate for the constituent logical elements of a quantum information processor. Over the past decade, spectacular improvements in the manufacturing and control of these devices have moved the superconducting qubit modality from the realm of scientific curiosity to the threshold of technical reality. In this talk, we present recent progress, challenges, and opportunities ahead in the engineering larger scale processors.
William D. Oliver is jointly appointed Professor of Electrical Engineering and Computer Science, Physics, and Lincoln Laboratory Fellow at the Massachusetts Institute of Technology. He serves as the Director of the Center for Quantum Engineering and as Associate Director of the Research Laboratory of Electronics. Will’s research interests include the materials growth, fabrication, design, and measurement of superconducting qubits, as well as the development of cryogenic packaging and control electronics.
Will is a Fellow of the American Physical Society, Senior Member of the IEEE, serves on the National Quantum Initiative Advisory Committee and the US Committee for Superconducting Electronics, and is an IEEE Applied Superconductivity Conference (ASC) Board Member. He received his PhD in Electrical Engineering from the Stanford University in 2003.
Cryogenic Electronics for Scalable Quantum Computing
Part I – Measurement Challenges:
Speaker: Dr. Jörgen Stenarson – Low Noise Factory
Scaling up quantum computers to thousands of qubits will push the design from using connectorized components to more integrated designs. This move increases the measurement challenges for the R&D phase as well as the production phase. Integration means that testing needs to be done at a circuit board interface instead of a coaxial interface. This leads to complications where the testing environment is different from the environment where it is going to be used. There is much larger difference in microstrip environments than in for example SMA connectors. At the same time there is a constant need to improve performance which means we also need to improve measurement uncertainty for all interesting parameters.
Dr Jörgen Stenarson received a PhD in Microwave Electronics in 2001 at Chalmers University of Technology, Gothenburg Sweden. In 2002 he joined SP (Technical Research Institute of Sweden) in 2002 where he was responsible for the VNA (Vector Network Analyzer) activities within the National Metrology Institute. In 2015 he joined Chalmers University of Technology to manage a 5M€ grant from the Wallenberg foundation to create a THz measurement infrastructure for the University. In 2017 he joined Low Noise Factory (LNF) as a lab manager, in 2019 he became the CTO of LNF. At LNF Jörgen returned to the subject of his PhD, cryogenic low noise amplifiers.
Cryogenic Electronics for Scalable Quantum Computing
Part II – Noise and Power Challenges:
Speaker: Dr. Arsalan Pourkabirian – Low Noise Factory
Another big challenge in cryogenic amplifiers is to reduce the noise and power dissipation, two factors which are crucial for qubit readout electronics. Transistors can be optimized for operation closer to the fundamental noise limit dictated by quantum mechanics and with much less power dissipation. In this talk, we present solutions to some of the problems associated with cryogenic transistors. We also present our recent progress on optimizing the InP HEMT for operation below 1 mW dc power dissipation.
Dr Arsalan Pourkabirian received his Ph.D. degree in microtechnology and nanoscience from the Chalmers University of Technology, Göteborg, Sweden, in 2014. In 2015 he joined the Microwave Electronic Laboratory in Chalmers University as a postdoctoral researcher, where he worked on cryogenic ultra-low noise amplifiers. In 2017 he joined Low Noise Factory (LNF) as a process engineer and later HEMT technology lead. His current research interests include cryogenic ultralow-noise InP high-electron mobility transistor devices and monolithic microwave integrated circuits.
Dilution Refrigerator Quantum Measurement Systems
Speaker: Dr. Russell Lake – Bluefors
Creating millikelvin temperatures remains a prerequisite for many methods of solid-state quantum information processing. This talk highlights recent advances towards improving and scaling up the cryogenic measurement infrastructure for quantum computing. Implementation of the input and output wiring presents specific technical challenges related to thermalization, routing of lines, non-reciprocal elements, and filtering, even for intermediate-scale quantum systems (e.g. 100 qubits). This talk highlights recent advances, benchmarking measurements that utilize superconducting circuits, and presents scaling strategies.
Dr. Russell E. Lake leads the research and development of quantum applications at Bluefors Oy in Helsinki, Finland. Dr. Lake has worked with cryogenic nano-electronics since 2012 and has previously held research appointments at the National Institute of Standards of Technology (Boulder, CO, USA), Lawrence Berkeley National Laboratory (Berkeley, CA, USA), and Aalto University (Finland). His team focuses on improving the cryogenic hardware of quantum computing through innovative measurements. Dr. Lake also oversees the technical direction of the Bluefors R&D hub at Quantum Delft on the TU-Delft Campus in the Netherlands.
Direct Digital Upconversion for High Fidelity Control of Qubits
Speaker: Nizar Messaoudi – Keysight Technologies
To manipulate qubits, classical electronics are required to generate and acquire a signals for control and readout, with differing requirements for each qubit technology. Typically, a quantum system necessitates several of these signals for each qubit with a high degree of synchronization and phase coherence, and increasingly needs real-time data processing and on-the-fly sequencing capabilities for feedback experiments. As the number of qubits scales beyond a hundred, the architecture of current control systems used will need to evolve to meet the increased demands for channel density. In this talk, we will explore how direct digital upconversion can significantly simplify some of the challenges that have plagued legacy control systems, such as mixer calibration and phase coherence. We will examine how an open FPGA architecture along with a rich quantum specific IP library enables dynamic quantum computing and Quantum Error Correction (QEC).
Nizar Messaoudi is the Solution Architect for the Quantum Engineering Solutions team at Keysight Technologies, Inc., where he is responsible for guiding the development of advanced, scalable electronic control systems for multiple qubit and quantum technologies. Prior to this, he worked as an RF Application Engineer at Keysight, supporting customers and enabling their success in several industries including Quantum Computing, 5G, Satellite Communications, and IoT. Before joining Keysight, he managed the undergraduate RF and microwave laboratory at the University of Waterloo.
Scalable Error Diagnostics, Benchmarking and Error Suppression for Large Quantum Processors
Speaker: Dr. Joseph Emerson – Keysight Technologies | Institute of Quantum Computing
This talk will describe our recent progress in developing more resource-efficient and impactful methods for tackling the challenge of scaling up quantum processors while scaling down error mechanisms. Our solutions lead to a compelling win-win situation where the very same methods that deliver enhanced error suppression during run-time also enable stable and predictable application-level benchmarking of holistic hardware and compiler performance for end-users.
Joseph Emerson is Head of Quantum Strategy at Keysight Technologies and a Professor at the Institute for Quantum Computing. Joseph, the former CEO and Founder of Quantum Benchmark Inc, is a leading researcher in error diagnostics, error suppression and performance benchmarking for quantum computing. He pioneered the randomized benchmarking method for detecting quantum computing error rates, now an industry standard, and his more recent work on randomized compiling and cycle benchmarking enables robust diagnoses of detailed error information, including cross-talk and spatial correlations, under arbitrary parallelized gate operations, to optimize device-design, pulse-engineering, and fault-tolerant performance.